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ltc4313-1/ltc4313-2/ ltc4313-3 1 4313123f typical a pplica t ion fea t ures descrip t ion 2-wire bus buffers with high noise margin the ltc ? 4313 is a hot swappable 2-wire bus buffer that provides bidirectional buffering while maintain- ing a low offset voltage and high noise margin up to 0.3 ? v cc . the high noise margin allows the ltc4313 to be interoperable with devices that drive a high v ol (>0.4v) and allows multiple ltc4313s to be cascaded. the ltc4313-1 and ltc4313-2 support level translation between 3.3v and 5v busses. in addition to these voltages, the ltc4313-3 also supports level translation to 1.5v, 1.8v and 2.5v. during insertion, the sda and scl lines are pre-charged to 1v to minimize bus disturbances. connection is established between the input and output after enable is asserted high and a stop bit or bus idle condition has been detected on the sda and scl pins. if both data and clock are not simultaneously high at least once in 45ms, the input is disconnected from the output. up to 16 clock pulses are subsequently generated to free the stuck bus. rise time accelerators (rtas) provide pull-up currents on sda and scl rising edges to meet rise time specifications in heavily loaded systems. the rtas are configured as slew limited switches in the ltc4313-1 and 2.5ma current sources in the ltc4313-2. the ltc4313-3 does not have rtas. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6356140, 6650174, 7032051, 7478286. 400khz operation a pplica t ions n bidirectional buffer increases fanout n high noise margin with v il = 0.3 ? v cc n compatible with non-compliant i 2 c devices that drive a high v ol n strong (ltc4313-1) and 2.5ma (ltc4313-2) rise t ime accelerator current n level shift 1.5v, 1.8v , 2.5v, 3.3v and 5v busses n prevents sda and scl corruption during live board insertion and removal from backplane n stuck bus disconnect and recovery n compatible with i 2 c, i 2 c fast mode and smbus n 4kv human body model esd ruggedness n high impedance sda, scl pins when unpowered n 8-lead msop and 8-lead (3mm 3mm) dfn packages n capacitance buffers/bus extender n live board insertion n telecommunications systems including atca n level translation n pmbus n servers ltc4313-1 gnd v cc 4313123 ta01a ready sclout sdaout enable sclin sdain scl1 sda1 2.7k2.7k 0.01f 3.3v ready scl2 sda2 1.3k10k 5v 1.3k 1v/div 500ns/div 4313123 ta01b r bus_in = 2.7k, c bus_in = 50pf r bus_out = 1.3k, c bus_out = 100pf sclout sclin
ltc4313-1/ltc4313-2/ ltc4313-3 2 4313123f p in c on f igura t ion a bsolu t e maxi m u m r a t ings supply voltage v cc ...................................... C0.3v to 6v input voltage enable .................................. C0.3v to 6v input/output v oltages sdain, sdaout, sclin, sclout ........................................... C0.3v to 6v output v oltage ready ................................. C0.3v to 6v output sink current ready ................................... 50ma (notes 1, 2) top view dd8 package 8-lead (3mm 3mm) plastic dfn 5 6 7 8 9 4 3 2 1enable sclout sclin gnd v cc sdaout sdain ready t jmax = 150c, ja = 39.7c/w exposed pad (pin 9) pcb connection to gnd is optional 1 2 3 4 enable sclout sclin gnd 8 7 6 5 v cc sdaout sdain ready top view ms8 package 8-lead plastic msop t jmax = 150c, ja = 163c/w o r d er i n f or m a t ion operating ambient temperature range l tc4313c ................................................ 0c to 70c ltc4313i .............................................. C40c to 85c s torage temperature range .................. C 65c to 150c lead temperature (soldering, 10 sec) ms package ...................................................... 300c lead free finish tape and reel part marking* package description temperature range ltc4313cdd-1#pbf ltc4313cdd-1#trpbf lfyz 8-lead (3mm 3mm) plastic dfn 0c to 70c ltc4313idd-1#pbf ltc4313idd-1#trpbf lfyz 8-lead (3mm 3mm) plastic dfn C40c to 85c ltc4313cms8-1#pbf ltc4313cms8-1#trpbf ltfyz 8-lead plastic msop 0c to 70c ltc4313ims8-1#pbf ltc4313ims8-1#trpbf ltfyz 8-lead plastic msop C40c to 85c ltc4313cdd-2#pbf ltc4313cdd-2#trpbf lfzb 8-lead (3mm 3mm) plastic dfn 0c to 70c ltc4313idd-2#pbf ltc4313idd-2#trpbf lfzb 8-lead (3mm 3mm) plastic dfn C40c to 85c ltc4313cms8-2#pbf ltc4313cms8-2#trpbf ltfzc 8-lead plastic msop 0c to 70c ltc4313ims8-2#pbf ltc4313ims8-2#trpbf ltfzc 8-lead plastic msop C40c to 85c ltc4313cdd-3#pbf ltc4313cdd-3#trpbf lgdd 8-lead (3mm 3mm) plastic dfn 0c to 70c ltc4313idd-3#pbf ltc4313idd-3#trpbf lgdd 8-lead (3mm 3mm) plastic dfn C40c to 85c ltc4313cms8-3#pbf ltc4313cms8-3#trpbf ltgdf 8-lead plastic msop 0c to 70c ltc4313ims8-3#pbf ltc4313ims8-3#trpbf ltgdf 8-lead plastic msop C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc4313-1/ltc4313-2/ ltc4313-3 3 4313123f e lec t rical c harac t eris t ics symbol parameter conditions min typ max units power supply/start-up v cc input supply voltage l 2.9 5.5 v v dd,bus 2-wire bus supply voltage ltc4313-1, ltc4313-2 l 2.9 5.5 v ltc4313-3 l 1.4 5.5 v i cc input supply current v enable = v cc = 5.5v, v sdain,sclin = 0v (note 3) l 6 8.1 10 ma i cc(disabled) input supply current v enable = 0v, v cc = 5.5v, v sdain,sclin = 0v l 2.5 3.5 4.5 ma v th_uvlo v cc uvlo threshold v cc rising l 2.55 2.7 2.85 v v cc_uvlo(hyst) uvlo threshold hysteresis voltage 200 mv v pre precharge voltage sda, scl pins open l 0.8 1 1.2 v buffers v os(sat) buffer offset voltage i ol = 4ma, driven v sda,scl = 50mv l 100 190 280 mv i ol = 500a, driven v sda,scl = 50mv l 15 60 120 mv v os buffer offset voltage i ol = 4ma, driven v sda,scl = 200mv l 50 120 180 mv i ol = 500a, driven v sda,scl = 200mv l 15 60 115 mv v il, falling buffer input logic low voltage v cc = 2.9v, 3.3v, 5.5v l 0.3 ? v cc 0.33 ? v cc 0.36 ? v cc v ?v il(hyst) v il hysteresis voltage 50 mv i leak input leakage current sda, scl pins = 5.5v, v cc = 5.5v, 0v l 10 a c in input capacitance sda, scl pins (note 4) l 10 pf rise time accelerators (ltc4313-1 and ltc4313-2 only) dv/dt (rta) minimum slew rate requirement sda, scl pins, v cc = 5v l 0.1 0.2 0.4 v/s v rta(th) rise time accelerator dc threshold voltage v cc = 5v l 0.38 ? v cc 0.41 ? v cc 0.44 ? v cc v ?v acc buffers off to accelerator on voltage sda, scl pins, v cc = 5v l 0.05?v cc 0.07?v cc mv i rta rise time accelerator pull-up current sda, scl pins, v cc = 5v (note 5) ltc4313-1 l 15 25 40 ma ltc4313-2 l 1.5 2.5 3.5 ma enable/control v en(th) enable threshold voltage l 1 1.4 1.8 v i leak enable leakage current v enable = 5.5v l 0.1 10 a v ready(ol) ready output low voltage i ready = 3ma, v cc = 5v l 0.4 v i ready(oh) ready off leakage current v cc = v ready = 5v l 0.1 5 a stuck low timeout circuitry t timeout bus stuck low timer l 35 45 55 ms i 2 c interface timing f scl(max) i 2 c frequency max l 400 khz t pdhl scl, sda fall delay v cc = v dd,bus = 5v, c bus = 100pf, r bus = 10k (note 4) 130 250 ns t f scl, sda fall times v cc = v dd,bus = 5v, c bus = 100pf, r bus = 10k (note 4) 20 300 ns t idle bus idle time l 55 95 175 s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 3.3v unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive and all voltages are referenced to gnd unless otherwise indicated. note 3: test performed with sda, scl buffers active. note 4: guaranteed by design and not tested. note 5: measured in a special dc mode with v sda,scl = v rta(th) + 1v. the transient i rta during rising edges for the ltc4313-1 will depend on the bus loading condition and the slew rate of the bus. the ltc4313-1s internal slew rate control circuitry limits the maximum bus rise rate to 75v/s by controlling the transient i rta .
ltc4313-1/ltc4313-2/ ltc4313-3 4 4313123f typical p er f or m ance c harac t eris t ics buffer dc i ol vs temperature t f (70% to 30%) vs bus capacitance t pdhl (50% to 50%) vs bus capacitance ltc4313-1 i rta vs temperature ltc4313-1 bus rise time (40% to 70%) vs c bus i cc enabled current vs supply voltage i cc disabled current vs supply voltage t a = 25c, v cc = 3.3v unless otherwise noted. v cc (v) 2 i cc (ma) 9.0 8.0 7.0 8.5 7.5 6.5 6.0 4 3 5 4313213 g01 6 3.5 2.5 4.5 5.5 v sdain,sclin = 0v v enable = 5.5v v cc (v) 2 i cc (ma) 4.0 3.0 3.5 2.5 2.0 4 3 5 2.5 4.5 3.5 5.5 4313213 g02 6 v sdain,sclin = 0v v enable = 0v temperature (c) ?50 i ol (ma) 12 5 6 11 10 4 8 9 7 0 50 4313213 g03 100 ?25 25 75 v sda,scl = 0.6v v sda,scl = 0.4v v os vs i bus for different driven voltage levels i bus (ma) 0 v os (mv) 250 200 150 0 50 100 1 3 4313213 g04 5 2 4 200mv 100mv driven v sda,scl = 50mv temperature (c) ?50 i rta (ma) 16 8 10 6 14 12 0 50 4313213 g05 100 ?25 25 75 v cc = v dd,bus v sda,scl = 0.6 ? v dd,bus c bus = 400pf, r bus = 10k 5v 3.3v c bus (pf) 0 t f (ns) 100 75 50 0 25 600 800 4313213 g06 1000 200 400 3.3v 5v v cc = v dd,bus r bus = 10k c bus (pf) 0 t pdhl (ns) 200 175 150 100 125 600 800 4313213 g07 1000 200 400 3.3v 5v v cc = v dd,bus r bus = 10k c bus (pf) 0 t rise (ns) 75 5v 3.3v 100 600 4313123 g08 50 25 200 400 800 v cc = v dd,bus
ltc4313-1/ltc4313-2/ ltc4313-3 5 4313123f p in func t ions enable (pin 1): connection enable input. when driven low, the enable pin isolates sdain and sclin from sdaout and sclout, asserts ready low, disables rise time accelerators and inhibits automatic clock and stop bit generation during a stuck low fault condition. when driven high, the enable pin connects sdain and sclin to sdaout and sclout after a stop bit or bus idle has been detected on both busses. driving enable high also enables automatic clock generation during a stuck low fault condition. during a stuck low fault condition, a rising edge on the enable pin forces a connection between sdain and sdaout and sclin and sclout. when using the ltc4313 in a hot swap? application with staggered connector pins, connect a 10k resistor between enable and gnd to ensure correct functionality. connect to v cc if unused. sclout (pin 2): serial bus 2 clock input/output. connect this pin to the scl bus segment where stuck low recovery is desired. connect an external pull-up resistor or current source between this pin and the bus supply. the bus supply needs to be v cc for the ltc4313-1 and ltc4313-2, but not for the ltc4313-3. refer to the applications informa - tion section for more details. do not leave open. sclin (pin 3): serial bus 1 clock input/output. connect this pin to the scl line on the upstream bus. connect an external pull-up resistor or current source between this pin and the bus supply. the bus supply needs to be v cc for the ltc4313-1 and ltc4313-2, but not for the ltc4313-3. refer to the applications information section for more details. do not leave open. gnd (pin 4): device ground. ready (pin 5): connection ready status output. this open drain n-channel mosfet output pulls low when the input and output sides are disconnected. ready is pulled high when enable is high and a connection has been established between the input and output. connect a pull-up resistor, typically 10k from this pin to the bus pull-up supply. leave open or tie to gnd if unused. sdain (pin 6): serial bus 1 data input/output. connect this pin to the sda line on the upstream bus. connect an external pull-up resistor or current source between this pin and the bus supply. the bus supply needs to be v cc for the ltc4313-1 and ltc4313-2, but not for the ltc4313-3. refer to the applications information section for more details. do not leave open. sdaout (pin 7): serial bus 2 data input/output. connect this pin to the sda bus segment where stuck low recovery is desired. connect an external pull-up resistor or current source between this pin and the bus supply. the bus supply needs to be v cc for the ltc4313-1 and ltc4313-2, but not for the ltc4313-3. refer to the applications informa - tion section for more details. do not leave open. v cc (pin 8): power supply voltage. power this pin from a supply between 2.9v and 5.5v. bypass with at least 0.01f to gnd. exposed pad (pin 9, dd8 package only): exposed pad may be left open or connected to device gnd.
ltc4313-1/ltc4313-2/ ltc4313-3 6 4313123f b lock diagra m 4313123 bd connect logic + ? + ? + ? + ? precharge 200k precharge connect precharge connect 200k 200k * * v cc i rta slew rate detector 0.2v/s slew rate detector 0.2v/s 200k slew rate detector 0.2v/s v cc i 2 c hot swap logic i 2 c hot swap logic rta_sdaout_en v il = 0.33 ? v cc rta_sclin_en rta_sdain_en rta_sclout_en v il = 0.33 ? v cc enable *inside dashed box applies only to the ltc4313-1 and ltc4313-2. ready gnd v cc + ? + ? 2.7v/2.5v 1.4v/1.3v uvlo 95s timer slew rate detector 0.2v/s i rta v cc i rta v cc i rta v il = 0.33 ? v cc v il = 0.33 ? v cc precharge connect connect 45ms timer sdain sclin sdaout sclout * *
ltc4313-1/ltc4313-2/ ltc4313-3 7 4313123f o pera t ion the ltc4313 is a high noise margin bus buffer which provides capacitance buffering for i 2 c signals. capacitance buffering is achieved by using back to back buffers on the clock and data channels which isolate the sdain and sclin capacitances from the sdaout and sclout capacitances respectively. all sda and scl pins are fully bidirectional. the high noise margin allows the ltc4313 to operate with non-compliant i 2 c devices that drive a high v ol , permits a number of ltc4313s to be connected in series and improves the reliability of i 2 c communications in large noisy systems. rise time accelerator (rta) pull-up currents (i rta ) turn on during rising edges to reduce bus rise time for the ltc4313-1 and ltc4313-2. in a typical application the input and output busses are pulled up to v cc although this is not a requirement. if v dd,bus is not tied to v cc , v dd,bus must be greater than v cc to prevent overdrive of the bus by the rtas for the ltc4313-1 and ltc4313-2. see the applications information section for v dd,bus requirements for the ltc4313-3. when the ltc4313 first receives power on its v cc pin, it starts out in an undervoltage lockout mode (uvlo) until its v cc exceeds 2.7v. the buffers and rtas are disabled and the ltc4313 ignores the logic state of its clock and data pins. during this time the precharge circuit forces a nominal voltage of 1v on the sda and scl pins through 200k resistors. once the ltc4313 exits uvlo and its enable pin has been asserted high, it monitors the clock and data pins for a stop bit or a bus idle condition. when a combination of either condition is detected simultaneously on the input and output sides, the ltc4313 activates the connection between sdain and sdaout, and sclin and sclout, respectively, asserts ready high and deactivates the precharge circuit. rtas for the ltc4313-1 and ltc4313-2 are also enabled at this time. when a sda/scl pin is driven below the v il level, the buffers are turned on and the logic low level is propagated though the ltc4313 to the other side. a high occurs when all devices on the input and output sides release high. once the bus voltages rise above the v il level, the buffers are turned off. the rtas are turned on at a slightly higher volt - age. the rtas accelerate the rising edges of the sda/scl inputs and outputs up to a voltage of 0.9?v cc , provided that the busses on their own are rising at a minimum rate of 0.4v/s as determined by the slew rate detectors. the rtas are configured to operate in a strong slew limited switch mode in the ltc4313-1 and in the current source mode in the ltc4313-2. the ltc4313 detects a bus stuck low (fault) condition when both clock and data busses are not simultaneously high at least once in 45ms. when a stuck bus occurs, the ltc4313 disconnects the input and output sides and after waiting at least 40s, generates up to sixteen 5.5khz clock pulses on the sclout pin and a stop bit to attempt to free the stuck bus. should the stuck bus release high during this period, automatic clock generation is terminated. once the stuck bus recovers, connection is re-established between the input and output after a stop bit or bus idle condition is detected. toggling enable after a fault condi - tion has occurred forces a connection between the input and output. when powering into a stuck low condition, the input and output sides remain disconnected even after the ltc4313 has exited the uvlo mode as a stop bit or bus idle condition is not detected on the stuck busses. after the timeout period, a stuck low fault condition is detected and the behavior is as described previously.
ltc4313-1/ltc4313-2/ ltc4313-3 8 4313123f the ltc4313 provides capacitance buffering, data and clock hot swap capability and level translation. the high noise margin of the ltc4313 permits interoperability with i 2 c devices that drive a high v ol permits series connec - tion of multiple ltc4313s and improves i 2 c communica- tion reliability. the ltc4313 isolates backplane and card capacitances and provides slew control of falling edges while level translating 3.3v and 5v busses. the ltc4313-1 and ltc4313-2 also provide pull-up currents to accelerate rising edges. these features are illustrated in the following subsections. rise time accelerator (rta) pull-up current strength (ltc4313-1 and ltc4313-2) after an input and output connection has been established, the rtas on both the input and output sides of the sda and scl busses are activated. during positive bus transi - tions of at least 0.4v/s, the rtas provide pull-up cur - rents to reduce rise time. the rtas allow users to choose larger bus pull-up resistors to reduce power consumption and improve logic low noise margins, design with bus capacitances outside of the i 2 c specification or to oper - ate at a higher clock frequency. the ltc4313-1 regulates its rta current to limit the bus rise rate to a maximum a pplica t ions i n f or m a t ion figure 1. bus rising edge for the ltc4313-1. v cc = v dd,bus = 5v figure 2. bus rising edge for the ltc4313-2. v cc = v dd,bus = 5v of 75v/s. the current is therefore directly proportional to the bus capacitance. the ltc4313-1 rta is capable of sourcing up to 40ma of current. rise time acceleration for the ltc4313-2 is provided by a 2.5ma current source. figures 1 and 2 show the rising waveforms of heavily loaded sdain and sdaout busses for the ltc4313-1 and ltc4313-2 respectively. in both figures, during a rising edge, the buffers are active and the input and output sides are connected, until the bus voltages on both the input and output sides are greater than 0.3 ? v cc . when each individual bus voltage rises above 0.41 ? v cc , the rta on that bus turns on. the effect of the acceleration strength is shown in the waveforms in figures 1 and 2 for identi- cal bus loads. the rtas of the ltc4313-1 and ltc4313-2 supply 10ma and 2.5ma of pull-up current respectively for the bus conditions shown in figures 1 and 2. for identical bus loads, the bus rises faster in figure 1 compared to figure 2 because of the higher i rta . the rtas are internally disabled during power-up and dur - ing a bus stuck low event. the rtas when activated pull the bus up to 0.9 ?v cc on the input and output sides of the sda and scl pins. in order to prevent bus overdrive by the rta, the bus supplies on the input and output sides 2v/div 1s/div 4313123 f01 v cc = v dd,bus = 5v r bus = 20k c in = c out = 200pf sdain sdaout 2v/div 1s/div 4313123 f02 v cc = v dd,bus = 5v r bus = 20k c in = c out = 200pf sdain sdaout
ltc4313-1/ltc4313-2/ ltc4313-3 9 4313123f of the ltc4313-1 and ltc4313-2 must be greater than or equal to 0.9 ? v cc . an example is shown in figure 3 where the input bus voltage is greater than v cc . during a rising edge, the input bus rise rate will be accelerated by the rta up to a voltage of 2.97v after which the bus rise rate will reduce to a value that is determined by the bus current and bus capacitance. the rta turn-off voltage is less than the bus supply and the bus is not overdriven. pull-up resistor value selection to guarantee that the rtas are activated during a rising edge, the bus must rise on its own with a positive slew rate of at least 0.4v/s. to achieve this, choose a maximum r bus using the formula: r b u s v dd ,b u s ( mi n ) ? v r t a (th ) ( ) 0.4 v s ? c b u s (1) r bus is the pull-up resistor, v dd,bus(min) is the minimum bus pull-up supply voltage, v rta(th) is the voltage at which the rta turns on and c bus is the equivalent bus capaci - tance. r bus must also be large enough to guarantee that: r b u s v dd ,b u s ( max) ? 0.4 v ( ) 4m a (2) this criterion ensures that the maximum bus current is less than 4ma. a pplica t ions i n f or m a t ion input to output offset voltage while propagating a logic low voltage on its sda and scl pins, the ltc4313 introduces a positive offset voltage between the input and output. when a logic low voltage 200mv is driven on any of the ltc4313s clock or data pins, the ltc4313 regulates the voltage on the opposite side to a slightly higher value. this is illustrated in equa - tion 3, which uses sda as an example: v s d a out = v s d ai n + 50m v + 15 ? ? v dd ,b u s r b u s (3) in equation 3, v dd,bus is the output bus supply voltage and r bus is the sdaout bus pull-up resistance. for driven logic low voltages < 200mv equation 3 does not apply as the saturation voltage of the open collector output transistor results in a higher offset. for a driven input logic low voltage below 220mv, the output is guaranteed to be below a v ol of 400mv for bus pull-up currents up to 4ma. see the typical performance characteristics section for offset variation as a function of the driven logic low voltage and bus pull-up current. figure 3. level shift application where the sdain and sclin bus pull-up supply voltage is higher than the supply voltage of the ltc4313 ltc4313-1 gnd v cc 4313123 f03 ready sclout sdaout enable sclin sdain scl1 sda1 r2 10k c1 0.01f r1 10k 5v ready scl2 sda2 r4 10k r3 10k 3.3v r5 10k
ltc4313-1/ltc4313-2/ ltc4313-3 10 4313123f a pplica t ions i n f or m a t ion falling edge characteristics the ltc4313 introduces a propagation delay on falling edges due to the finite response time and the finite current sink capability of the buffers. in addition the ltc4313 also slew limits the falling edge to an edge rate of 45v/s (typ). the slew limited falling edge eliminates fast transitions on the busses and minimizes transmission line effects in systems. refer to the typical performance characteristics section for the propagation delay and fall times as a func - tion of the bus capacitance. stuck bus disconnect and recovery during an output bus stuck low condition (sclout and sdaout have not been simultaneously high at least once in 45ms), the ltc4313 attempts to unstick the bus by first breaking the connection between the input and output. after 40s the ltc4313 generates up to sixteen 5.5khz clock pulses on the sclout pin. should the stuck bus release high during this period, clock generation is stopped and a stop bit is generated. this process is shown in figure 4 for the case where sdaout starts out stuck low and then recovers. as seen from figure 4, the ltc4313 pulls ready low and breaks the connection between the input and output sides, when a stuck low condition on sda is detected. clock pulses are then issued on sclout to at - tempt to unstick the sdaout bus. when sdaout recovers, clock pulsing is stopped, a stop bit is generated on the output and ready is released high. when powering up into a stuck low condition, a connection is never made between the input and the output, as a stop bit or bus idle condition is never detected. after a timeout period of 45ms, the behavior is the same as described previously. figure 4. bus waveforms during sdaout stuck low and recovery event 4313123 f04 sclout 5v/div ready 5v/div sdain 5v/div sdaout 5v/div 1ms/div disconnect at timeout stuck low > 45ms automatic clocking recovers high driven low stop bit generated
ltc4313-1/ltc4313-2/ ltc4313-3 11 4313123f a pplica t ions i n f or m a t ion live insertion and capacitance buffering application figure 5 illustrates an application of the ltc4313 that takes advantage of the ltc4313s hot swap, capacitance buffer - ing and precharge features. if the i/o cards were plugged directly into the backplane without ltc4313 buffers, all of the backplane and card capacitances would directly add together, making rise time requirements difficult to meet. placing an ltc4313 on the edge of each card isolates the card capacitance from the backplane. for a given i/o card, the ltc4313 drives the capacitance of everything on the card and the devices on backplane must drive only the small capacitance of the ltc4313 which is < 10pf. in figure 5 a staggered connector is used to connect the ltc4313 to the backplane. v cc and gnd are the longest pins to ensure that the ltc4313 is powered and forcing a 1v precharge voltage on the medium length sda and scl pins before they contact the backplane. the 1v pre- charge voltage is applied to the sda and scl pins through 200k resistors. since cards are being plugged into a live backplane whose sda and scl busses could be at any voltage between 0 and v cc , precharging the ltc4313s sda and scl pins to 1v minimizes disturbances to the backplane bus when cards are being plugged in. the low (< 10pf) input capacitance of the ltc4313 also contributes to minimizing bus disturbance as cards are being plugged in. with enable being the shortest pin and also pulled to gnd by a resistor, the staggered approach provides ad - ditional time for transients associated with live insertion to settle before the ltc4313 can be enabled. a 10k or lower pull-down resistor from enable to gnd is recommended. if a connector is used where all pins are of equal length, the benefit of the precharge circuit is lost. also, the enable signal to the ltc4313 must be held low until all the transients associated with card insertion into a live system die out. level translating to voltages < 2.9v (ltc4313-3 only) the ltc4313-3 can be used for level translation to bus voltages below 2.9v. since the maximum buffer turn-on and turn-off voltages are 0.36 ? v cc , the minimum bus supply voltage is determined by the following equation, v dd ,b u s ( mi n ) 0.36 ? v cc 0.7 (4) in order to meet the v ih = 0.7 ? v dd,bus requirement and not impact the high side noise margin. users willing to live with a lower logic high noise margin can level translate down to 1.4v. an example of voltage level translation from 3.3v to 1.8v is illustrated in figure 6, where a 3.3v input voltage bus is translated to a 1.8v output voltage bus. tying v cc to 3.3v satisfies equation 4. a similar voltage translation can also be performed going from a 3.3v bus supply on the output side to a 1.8v input if the v cc pin of the ltc4313-3 is tied to the 3.3v output supply.
ltc4313-1/ltc4313-2/ ltc4313-3 12 4313123f a pplica t ions i n f or m a t ion figure 5. ltc4313 in an i 2 c hot swap application with a staggered connector r6 10k r4 10k r5 10k ltc4313 gnd v cc sclout sdaout ready sclin sdain enable c2 0.01f card 1_scl card 1_sda card n_scl card n_sda c1 0.01f r9 10k 4313123 f05 r7 10k i/o peripheral card n i/o peripheral card 1 card connector backplane connector r8 10k ltc4313 gnd v cc sclout sdaout ready sclin sdain enable c4 0.01f c3 0.01f r3 10k r1 10k r2 10k ready scl sda enable 1 5v 3.3v enable n ? ? ? ? ? ? figure 6. voltage level translation from 3.3v to 1.8v using the ltc4313-3 ltc4313-3 gnd v cc 4313123 f06 ready sclout sdaout enable sclin sdain scl1 sda1 r2 10k r5 10k r4 10k r3 10k r1 10k 3.3v ready scl2 sda2 1.8v c1 0.01f
ltc4313-1/ltc4313-2/ ltc4313-3 13 4313123f a pplica t ions i n f or m a t ion telecommunications systems the ltc4313 has several features that make it an excellent choice for use in telecommunication systems such as atca. referring to figures 7 and 8, buffers are used on the edges of the field replaceable units (fru) and shelf managers to shield devices on these cards from the large backplane capacitance. the input capacitance of the ltc4313 is less than the 10pf maximum specification for buffers used in bussed atca applications. the ltc4313 buffers can drive capacitances >1nf, which is greater than the maximum backplane capacitance of 690pf in bussed atca systems. the precharge feature, low input capacitance and high impedance of the sda and scl pins of the ltc4313 when it is unpowered, minimize disturbances to the bus when cards are being hot swapped. in figure 7, the rta of the ltc4313-2 on the shelf manager supplies sufficient pull- up current, allowing the 1s rise time requirement to be met on the heavily loaded backplane for loads well beyond the 690pf maximum specification. the 0.33 ? v cc turn-off voltage of the ltc4313s buffers provides a large logic low noise margin in these systems. in the bussed atca application shown in figure 7, the ltc4313s located on the shelf managers #1 and #2 and on the frus, drive the large backplane capacitance while the microcontrollers on the shelf managers and the i 2 c slave devices on the frus drive the small input capacitance of the ltc4313-3. figure 7. ltc4313s used in a bussed atca application. only the clock path is shown for simplicity ltc4313-2 p v cc 3.3v sclout sclin enable r1 10k r2 2.7k 4313123 f07 backplane ipmb-a scl ipmb-b scl shelf manager #1 shelf manager #2 identical to shelf manager #1 to shmc#2 to shmc#2 ipmb-b ipmb-b details (not shown) are identical to ipmb-a fru #1 ltc4313-3 i 2 c device 3.3v 3.3v sclout v cc sclin r3 10k r4 10k ltc4313-3 sclout v cc sclin fru #n ltc4313-3 i 2 c device 3.3v 3.3v sclout v cc sclin r6 10k r5 10k ltc4313-3 sclout v cc sclin ? ? ?
ltc4313-1/ltc4313-2/ ltc4313-3 14 4313123f a pplica t ions i n f or m a t ion the ltc4313-2 on only one of the shelf managers is enabled at any given time. the hot insertion logic on the ltc4313-3 allows the frus to be plugged or unplugged from a live backplane. the features mentioned previously provide noise immunity and allow timing specifications to be met for a wide range of backplane loading conditions. in the 6 4 radial configuration shown in figure 8, the ltc4314s on the shelf managers and the ltc4313-2s on the frus drive the large backplane capacitance while the i 2 c slave devices on the frus only drive the small input capacitance of the ltc4313-2s. the ltc4314s on only one of the shelf managers are enabled at a given time. all the benefits provided by the ltc4313-2 in figure 7 apply to figure 8 as well. cascading and interoperability with other ltc buffers and non-compliant i 2 c devices multiple ltc4313s can be cascaded or the ltc4313 can be cascaded with other ltc bus buffers. cascades often exist in large i 2 c systems, where multiple i/o cards having bus buffers connect to a common backplane bus. two issues need to be considered when using such cascades C the additive nature of the buffer logic low offset voltages and the impact of the rta-buffer interaction on the noise margin. figure 8. ltc4313-2 used in a radially connected telecommunication system in a 6 4 arrangement. only the clock path is shown for simplicity. the data pathway is identical shelf manager #1 ipmb-a(x24) ipmb-b(x24) scl1 scl24 scl1 scl24 3.3v r2 10k ltc4314#1 v cc v cc2 sclout1 sclout2 sclout3 sclout4 sclin enable1 enable2 enable3 enable4 acc enable1a enable2a enable3a enable4a enable21a enable22a enable23a enable24a r1 10k p 3.3v 3.3v ipmb-b details (not shown) are identical to ipmb-a ipmb-b r5 10k ltc4314#6 v cc v cc2 sclout1 sclout2 sclout3 sclout4 sclin enable1 enable2 enable3 enable4 acc 3.3v 4313123 f08 backplane ipmb-b scl24 3.3v ipmb-a scl1 ipmb-a scl24 ipmb-b scl1 fru #1 ltc4313-2 i 2 c device 3.3v sclout v cc sclin r3 10k r4 10k ltc4313-2 sclout v cc sclin fru #24 3.3v ltc4313-2 i 2 c device 3.3v sclout v cc sclin r6 10k r7 10k ltc4313-2 sclout v cc sclin shelf manager #2 identical to shelf manager #1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
ltc4313-1/ltc4313-2/ ltc4313-3 15 4313123f a pplica t ions i n f or m a t ion first, when two or more buffers are connected in a cas - cade configuration, if the sum of the offsets across the cascade (refer to equation 3 and the data sheets of the corresponding buffers) plus the worst-case driven logic low voltage exceeds the minimum buffer turn-off voltage, signals will not be propagated across the cascade. the maximum driven logic low voltage must be set accordingly, for correct operation in such cascades. second, noise margin is affected by cascading the ltc4313 with buffers whose rta turn-on voltage is lower than the ltc4313 buffer turn-off voltage. the v il for the ltc4313 is set to 0.3 ? v cc to achieve high noise margin provided that the ltc4313 buffers do not contend with rtas of other products. to maximize logic low noise margin, dis - able the rtas of the other ltc buffers if possible and use the rtas of the ltc4313 in cascading applications. to permit interoperability with other ltc buffers whose rtas cannot be disabled, the ltc4313 senses the rta current and turns off its buffers below 0.3 ? v cc . this eliminates contention between the ltc4313 buffers and other rtas, making the sda/scl waveforms monotonic. figures 9 shows the ltc4313-1 operating on a bus shared with ltc4300a and ltc4307 buffers. the correspond - ing scl waveforms are shown in figure 10. the rtas on the ltc4300a and the ltc4307 cannot be disabled. the backplane in figure 9 has five i/o cards connected to it. each i/o card has a ltc bus buffer on its outside edge for sda/scl hot swap onto the backplane. in this example, there are three ltc4300as, one ltc4307 and one ltc4313-1. the scl1 bus is driven by an i 2 c master (master not shown). when the scl2 voltage crosses 0.6v and 0.8v, the rtas on the ltc4300a and ltc4307 turn on respectively and source current into scl2. the ltc4313-1 detects this and turns off its buffers, releasing scl1 and scl2 high. contention between the ltc4313-1 buffers and the ltc4300a and ltc4307 rtas is prevented and the scl1, scl2 and scl3 waveforms in figure 10 are monotonic. the logic low noise margin is reduced because the ltc4313-1 buffers turn off when the scl1 voltage is approximately 0.6v. generally, noise margin will be reduced if other rtas turn on at a voltage less than 0.3 ? v cc . the reduction in noise margin is a function of the number of ltc4313s and the number and turn-on voltage of other rtas, whose current must be sunk by the ltc4313 buffers. the same arguments apply for non-ltc buffer products whose rta turn-on voltage is less than 0.3 ? v cc . interoperability is improved by reducing the interaction time between the ltc4313 buffers and other rtas by reducing r1 and c b1 . the following guidelines are recommended for single supply systems, a. for 5v systems choose r1 < 20k and c b1 < 1nf. there are no other constraints. b. for 3.3v systems, refer to figures 11 and 12 for opera - tion with ltc4300as and ltc4307s. in the figures, m = number of ltc4300 a s or ltc430 7 s number of ltc4313s r1 and c b1 must be chosen to be below the curves for a specific value of m. for m greater than the val - ues shown in the figures, non-idealities do not result. r1 <20k and c b1 <1nf are still recommended. the ltc4313 is interoperable with non-compliant i 2 c devices that drive a high v ol > 0.4v. figure 13 shows the ltc4313-1 in an application where a microcontroller com - municates through the ltc4313-1 with a non-compliant i 2 c device that drives a v ol of 0.6v. the ltc4313 buffers are active up to a bus voltage of 0.3 ? v cc which is 1.089v in this case, yielding a noise margin of 0.489v. repeater application multiple ltc4313s can be cascaded in a repeater applica - tion where a large 2-wire system is broken into smaller sections as shown in figure 14. the high noise margin and low offset of the ltc4313 allows multiple devices to be cascaded while still providing good system level noise margin. in the repeater circuit shown in figure 14 if scl1/sda1 is driven externally to 200mv, scl2/sda2 is regulated to ~440mv worst-case by the cascade of ltc4313-1s. the buffer turn-off voltage is 1.089v, yield - ing a minimum logic low noise margin of ~650mv. in figure 14, use of the rtas combined with an increased level of buffering reduces transition times and permits operation at a higher frequency.
ltc4313-1/ltc4313-2/ ltc4313-3 16 4313123f a pplica t ions i n f or m a t ion figure 9. the ltc4313-1 operating in a cascade with other ltc buffers with active rtas. only the clock pathway is shown for simplicity ltc4313-1 gnd v cc sclout sclin scl1 scl2 r1 5k c1 0.01f 3.3v ltc4300a gnd v cc sclout scl3 sclin r3 2.7k 5v r2 2.7k 4313123 f09 c b1 100pf * c b2 690pf ltc4307 gnd v cc sclout scl4 i/o card #5 i/o card #2-4 sclin r4 5k backplane i/o card #1 * parasitic backplane capacitance figure 10. corresponding scl switching waveforms. no glitches are seen 2v/div 2v/div 2v/div 1s/div 4313123 f10 ltc4300a/ ltc4307 rtas turn on ltc4313 buffers turn off ltc4313-1 rta on scl2 scl3 scl1
ltc4313-1/ltc4313-2/ ltc4313-3 17 4313123f a pplica t ions i n f or m a t ion figure 11. recommended maximum r1 and c b1 values for the ltc4313 operating with multiple ltc4300as in a 3.3v system figure 12. recommended maximum r1 and c b1 values for the ltc4313 operating with multiple ltc4307s in a 3.3v system figure 14. ltc4313-1s in a repeater application r bus (k) 0 c bus (pf) 100 1000 8 4313123 f11 10 2 64 10 m = 1 m = 2 m = 3 r bus (k) 0 c bus (pf) 1000 10000 8 4313123 f12 100 2 64 10 m = 1 ltc4313-1 gnd v cc 4313123 f14 ready sclout sdaout enable sclin sdain scl1 sda1 r2 10k r3 10k r4 10k r1 10k c1 0.01f 3.3v ltc4313-3 gnd v cc ready sclout sdaout enable sclin sdain ltc4313-1 gnd v cc ready sclout sdaout enable sclin sdain r6 10k r5 10k r9 10k r8 10k r7 10k scl2 sda2 figure 13. communication with a non-compliant i 2 c device using the ltc4313 ltc4313 gnd v cc 4313123 f13 sclout sdaout discen enable ready sclin sdain r5 10k r3 10k r2 10k r1 10k r4 10k c1 0.01f non-compliant i 2 c device v ol = 0.6v 5v 3.3v p
ltc4313-1/ltc4313-2/ ltc4313-3 18 4313123f p ackage descrip t ion dd8 package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698 rev c) 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 ? 0.05 (dd8) dfn 0509 rev c 0.25 0.05 2.38 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 1.65 0.05 (2 sides) 2.10 0.05 0.50 bsc 0.70 0.05 3.5 0.05 package outline 0.25 0.05 0.50 bsc please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc4313-1/ltc4313-2/ ltc4313-3 19 4313123f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev f) msop (ms8) 0307 rev f 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 ? 6 typ detail ?a? detail ?a? gauge plane 1 2 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc4313-1/ltc4313-2/ ltc4313-3 20 4313123f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2011 lt 1011 ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments LTC4300A-1/ ltc4300a-2/ ltc4300a-3 hot swappable 2-wire bus buffers -1: bus buffer with ready and enable -2: dual supply buffer with acc -3: dual supply buffer and enable ltc4302-1/ ltc4302-2 addressable 2-wire bus buffer address expansion, gpio, software controlled ltc4303/ ltc4304 hot swappable 2-wire bus buffer with stuck bus recovery provides automatic clocking to free stuck i 2 c busses ltc4305/ ltc4306 2- or 4-channel, 2 wire bus multiplexers with capacitance buffering two or four software selectable downstream busses, stuck bus disconnect, rise time accelerators, fault reporting, 5kv hbm esd ltc4307 low offset hot swappable 2-wire bus buffer with stuck bus recovery 60mv bus offset, rise time accelerators, 5kv hbm esd ltc4307-1 high definition multimedia interface (hdmi) level shifting 2-wire bus buffer 60mv buffer offset, 3.3v to 5v level shifting, 30ms stuck bus d isconnect and recovery, 5kv hbm esd ltc4308 low voltage, level shifting hot swappable 2-wire bus buffer with stuck bus recovery bus buffer with 1v precharge, enable and ready, 0.9v to 5.5v level translation, 30ms stuck bus disconnect and recovery, output side rise time accelerators, 6kv hbm esd ltc4309 low offset hot swappable 2-wire bus buffer with stuck bus recovery 60mv buffer offset, 30ms stuck bus disconnect and recovery, rise time accelerators, 5kv hbm esd, 1.8v to 5.5v level translation ltc4310-1 ltc4310-2 hot swappable i 2 c isolators bidirectional i 2 c communication between two isolated busses, ltc4310-1: 100khz bus, ltc4310-2: 400khz bus ltc4311 low voltage i 2 c/smbus accelerator rise time acceleration with enable and 8kv hbm esd ltc4312/ ltc4314 2- or 4-channel, hardware selectable 2 wire bus multiplexers with capacitance buffering two or four pin selectable downstream busses, v il up to 0.3 ? v cc , stuck bus disconnect, rise time accelerators, 45ms stuck bus disconnect and recovery, 4kv hbm esd ltc4315 high noise margin 2-wire bus buffer v il = 0.3 ? v cc , rise time accelerators, stuck bus disconnect, 1v precharge, enable and ready pins, 4kv hbm esd cascaded application with level shifting and operation with a non-compliant i 2 c device ltc4313-3 gnd v cc 4313123 ta02 ready sclout sdaout enable sclin sdain scl1 sda1 scl2 sda2 r2 10k r3 10k r4 10k r1 10k c1 0.01f 2.5v 3.3v 5v ltc4313-2 gnd backplane or long cable run v cc ready sclout sdaout enable sclin sdain r7 10k r6 10k r5 10k non-compliant i 2 c device v ol = 0.6v

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